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Posted by / 16-Aug-2020 09:29

Validating memory

I am happy to report that such tools are now becoming available, for example, from Peter Sewell and Susmit Sarkar at the University of Cambridge, Luc Maranget, Francesco Zappa Nardelli, and Pankaj Pawan at INRIA, and Jade Alglave at Oxford University.This group has done some excellent work over the past few years formalizing memory models for real computer systems, including that of ARM, Power, some additional 64-bit members of the Power family, x86 (and yes, academics consider x86 to be a weak-memory system), and C/C 11's new memory model.Something else you could do is write the validation file manually prior to a maintenance based on some gathered data from the network and on your expectations.You could, then, perform your changes and use this tool to verify the state of the network is exactly the one you wanted.The report will let you know a method wasn’t executed in the following manner: As mentioned in the introduction, this is interesting to validate state.

:-) I have yet to see a definition of the MIPS memory-ordering model, but I do hope to at some point.To do that, you can write a YAML file describing the state you expect your devices to be in and tell napalm to retrieve the state of the device and build a compliance report for you.As always, with napalm, doing this is very easy even across multiple vendors : ) Writing validators files that can be interpreted by napalm is very easy.Given such a guarantee, the developer could then be reasonably confident that this code sequence would operate correctly on all current and future versions of the hardware in question.Previous LWN articles (here and here), as well as Mathieu Desnoyers's doctoral dissertation [PDF], describe how to use search the code fragments' full state space, the developer can be reasonably confident that the code fragments will operate correctly on real hardware.

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Until then, I have no idea, but MIPS is rumored to have a weak memory model similar to ARM and Power PC.

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